1. Field of the Invention
This invention generally relates to digital circuits and in particular to any collection of digital logic, such as in an IC, where power reduction is desired.
2. Description of the Related Art
Power dissipation is becoming a limiting factor in VLSI design as technologies scale down and complexity grows. Leakage, speed increases, and other effects are increasing the amount of power dissipated in integrated circuits (ICs).
Digital logic typically comprises the greatest part of modem ICs and so techniques to reduce the power dissipation of digital circuits typically have relatively large impact on the industry. When considering power dissipation techniques, it is important to note the relationship between the speed and power of a digital path.
As the required speed of a logic path increases, the power dissipated will typically increase. In other words, as the required path delay is decreased, the power dissipated will typically increase. In CMOS processes, this can be the result of several phenomenon: Non-topological techniques to achieve a faster path, i.e., a path with less delay, is usually achieved with larger devices, or lower threshold voltage devices, or devices with forward biased bodies; or some combination of the foregoing. These techniques typically result in greater power dissipated.
There are relatively many logic paths in a typical integrated circuit, and to reach a certain level of overall speed performance for an IC, each logic path should have a delay not exceeding a specified amount. In a synchronous design, the specified maximum path delay is typically the period of a specified system clock signal minus a margin to account for setup times.
Digital logic circuits are usually synthesized from a finite set of logic gates, e.g., from a standard cell library. This finite set of logic gates can include, for example, NAND gates, NOR gates, inverters, flip flops, and the like. Each logic gate usually has a small discrete set of alternatives to achieve various performance objectives such a speed and power. An inverter, for example, may have alternatives with varying drive strengths; which, in the case of the inverter, simply can be implemented with larger or smaller transistors so that the smallest, lowest power inverter can be used in a given application. In another example, the inverter may be available in both high threshold voltage (Vt) and low Vt versions. In the conventional art, there is only a discrete set of such alternatives. The geometry of the transistors or the threshold voltage of the transistors is not variable.
As logic synthesis proceeds, instances of the logic gates are chosen and connected together to achieve some logic function with a delay less than a specified maximum. As used herein, a logic “path” includes the gates and connections from inputs to outputs of a logic function. The delay of the path is the time from the earliest assertion at an input to the last assertion by an output. After logic synthesis is complete, a histogram of all the logic path delays can be generated as shown in FIG. 1. The longest delay is called the “critical path.” The delay of the critical path should be less than the specified maximum in order for the overall digital logic section to meet the integrated circuit (IC) performance specification.
FIG. 1 is a histogram generally illustrating a distribution of delay paths with a relatively broad distribution. The limited choices available to an IC designer of digital circuits from a fixed set of logic gates typically results in a path delay histogram with relatively broadly distributed paths, rather than narrowly distributed. The histogram below shows a spread of faster paths and slower paths. When there is an inverse relationship between path delay and potential path power consumption, the presence of paths faster (less time) than the critical path indicates that slower and lower power consuming circuits can be used. Typically, the paths that are faster, that is, shorter delay, than the “max delay allowed” are potentially wasting power.